Chapter 6
Multi-core processor
A multi-core processor is a single computing component with two or more independent actual processors called "cores", (which are the units that read and execute program instructions).1 The instruction tells the processor what to do such as reading data from memory or sending data to the user display, so rapidly that human perception experiences the results as the smooth operation of a program. The cores are part of a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package.
A many-core processor is a multi-core processor in which the number of cores is large enough that traditional multi-processor techniques are no longer efficient because of congestion in supplying instructions and data to the many processors ( range of several tens of cores; above this network on chip technology prevails). Tilera processors feature a switch in each core to route data through an on-chip mesh network to solve congestion, enabling their core count to scale up to 100 cores.
A dual-core processor has two cores (e.g. AMD Phenom II X2, Intel Core Duo), a quad-core processor contains four cores (e.g. AMD Phenom II X4, the Intel 2010 core line that includes three levels of quad-core processors, see i3, i5, and i7 at Intel Core), and a hexa-core processor contains six cores (e.g. AMD Phenom II X6, Intel Core i7 Extreme Edition 980X). A multi-core processor implements multiprocessing in a single physical package. Designs include tightly or loosely coupled devices that share caches, and use message passing or shared memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores, heterogeneous multi-core systems are not identical.
The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms, possible gains are limited by the fraction of the software that can be parallelized to run on multiple cores simultaneously (Amdahl's law). Most applications require effort in re-factoring the whole problem which make speed prohibitive.2
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